Conventionally to improve the static noise margin of an SRAM bit cell, a wordline underdrive scheme through a read assist circuit is employed to meet cells hold stability. However, this scheme degrades the write margin of the cells resulting in write failures when operated in low voltage (VDDMIN) environment. State-of-the-art SRAM try to improve the write margin either through a negative bitline or wordline overdrive write assist circuits in the low voltage VDDMIN environment. Essentially, write assist circuits employ voltage boosting which overdrives the pass gate of a bit cell to improve the write margin. But at higher voltage operations, voltage boosting through a write assist circuit would cross the maximum allowable technology voltage and will have a detrimental effect on bit cells pass gate oxide tox reliability like hot carrier injection and time-dependent dielectric breakdown.
It is desirable to provide an integrated circuit for storing data which allows to improve the write margin in a low operating voltage environment.